Übersetzung für 'address bus' von Englisch nach Deutsch

address bus

Adressbus {m}

Adresspfad {m}

Adreßbus {m} [alt]

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bus address register

Busadressregister {n}

Busadreßregister {n} [alt]

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low-entry bus <LE bus>

Tiefeinstiegsbus {m}transp.

Low-Entry-Bus {m} <LE-Bus> [Niederflurtechnik]transp.

one-and-a-half decker (bus) <1½-decker bus>

Anderthalbdecker {m} <1 ½-Decker> [Omnibus]automot.transp.

Eineinhalbdecker {m} <1 ½-Decker> [Omnibus]automot.transp.

one-and-a-half deck bus <1½-deck bus>

Eineinhalbdecker {m} <1 ½-Decker> [Omnibus]automot.transp.

bus

Sammelweg {m}

Datenleitung {f}comp.

Datensammelweg {m}comp.

Datenbus {m}comp.

Sammelschiene {f}electr.

Autobus {m} [seltener] [Bus]transp.

Sammelleitung {f}

Vielfachleitung {f}

Stadtomnibus {m}traffictransp.

Bus {m}comp.transp.

Kanal {m}

bus terminator

Busabschlussschaltung {f}electr.

bus driver

Buschauffeur {m} [bes. schweiz.]jobs

bus configuration

Busanordnung {f}comp.electr.

bus width

Busbreite {f}comp.electr.

• The address bus used 30-bits (A31..A2) complemented by four byte-select pins (instead of A0,A1) to allow for any 8/16/32-bit selection.
• The 8080's 40-pin DIP packaging permits it to provide a 16-bit address bus and an 8-bit data bus, enabling access to 64 KiB (216 bytes) of memory.
• To allow it to fit into a 40-pin dual in-line package (DIP) chip, the address bus and data bus shared a set of 16 pins.
• Typically two additional pins in the control bus -- a row-address strobe (RAS) and the column-address strobe (CAS) -- are used to tell the DRAM whether the address bus is currently sending the first half of the memory address or the second half.
• It is actually two buses (not on the diagram): an address bus and a data bus.

• Parallel EEPROM devices typically have an 8-bit data bus and an address bus wide enough to cover the complete memory.
• The address bus is typically a double octet (16 bits) wide, due to practical and economical considerations.
• The content of the refresh register R is sent out on the lower half of the address bus along with a refresh control signal while the CPU is decoding and executing the fetched instruction.
• In addition, the address bus can be made tristate and the CPU can be halted cleanly.
• A further extended version, which exposes 31 bits of the address bus, was also produced in small quantities as the 68012.