Übersetzung für 'mask instruction' von Englisch nach Deutsch

mask instruction

Ausblendbefehl {m}

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continuous positive airway pressure mask <CPAP mask>

CPAP-Maske {f}med.MedTech.

Werbung

to mask

verdecken

blenden [abdecken]constr.

maskieren

vertäuben [Audiometrie]audio

verbergen

kaschieren

mask

Schablone {f}

Maske {f}

Masque {f}mus.

Abdeckung {f}

carnival mask

Karnevalsmaske {f}

mask image

Leerbild {n} [Maskenbild]MedTech.

mask run

Maskenlauf {m} [ohne Kontrastmittel]MedTech.

life mask

Lebendmaske {f}

mummy mask

Mumienmaske {f}archaeo.art

golden mask

Goldmaske {f}archaeo.art

ancestral mask

Ahnenmaske {f}ethn.

dust mask

Staubmaske {f}

goalie mask

Torwartmaske {f} [Eishockey]sports

• Some SIMD instruction sets, like AVX2, have the ability to use a logical mask to conditionally load/store values to memory, a parallel form of the conditional move, and may also apply individual mask bits to individual arithmetic units executing a parallel operation.
• At the same time Plessey in the UK released NMOS processors numbered PIC1650 and PIC1655 based on the GI design, using the same instruction sets, either user mask programmable or versions pre-programmed for auto-diallers and keyboard interfaces.
• The operating system could somewhat manage the ordering of interrupts by setting an interrupt mask using the MSKO instruction.
• ] instruction), Vector processors produce much more compact code because they do not need to perform explicit mask calculation to cover the last few elements (illustrated below).
• Depending on the vector register and element widths, only a subset of bits of the mask register may be used by a given instruction.

• The DAP had a Single Instruction Multiple Data (SIMD) architecture.
• The superintendent stated that she would prefer that in-person instruction remain.
• Finally, the system also included a 64-bit real-time clock register and four 64-bit instruction buffers that held sixty-four 16-bit instructions each.
• The Univac 1100/2200 used the "partial word designator" of the instruction, the "J" field, to access characters.
• The microprocessor is tuned at a clock frequency of 8 megahertz and supports the Intel 8088 instruction set.

• Such an instruction had obvious implications on the staffing of the HPC, which was reluctantly allowed to increase its establishment to accommodate the extra work.
• However, the VEX coding scheme has been used for other instruction types as well in subsequent expansion of instruction set.
• One can also prevent the bug by disabling implicit bus locking normally done by xchg instruction. This is accomplished by setting bit four (mask of [...]) in the configuration register, [...].