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 Übersetzung für 'non maskable interrupt' von Englisch nach Deutsch
comp.
non-maskable interrupt
nicht maskierbarer Interrupt {m}
comp.
non-maskable interrupt <NMI>
nichtmaskierbare Unterbrechung {f}
Teiltreffer
non-maskable {adj}nichtmaskierbar
comp.
software interrupt <SW interrupt>
Softwareinterrupt {m} <SW-Interrupt> [auch: Software-Interrupt]
comp.
hardware interrupt <HW interrupt>
Hardwareinterrupt {m} <HW-Interrupt> [auch: Hardware-Interrupt]
maskable {adj}maskierbar
maskable interruptsmaskierbare Unterbrechungen {pl}
interruptUnterbrechung {f}
167
to interrupthineinreden [unterbrechen]
34
to interruptstören
277
interruptVerarbeitungs­unterbrechung {f}
6
to interrupttrennen
27
to interruptunterbrechen
3867
to interrupthindern
42
no-interrupt {adj}interruptfrei
process interruptProzeßunterbrechung {f}
interrupt conditionUnterbrechungs­bedingung {f}
interrupt indicationUnterbrechungs­anzeige {f}
interrupt decoderUnterbrechungs­analyseroutine {f}
to interrupt sb.jdn. unterbrechen
137
interrupt analysisUnterbrechungs­analyse {f}
to interrupt [conversation]dazwischenreden
43
22 Übersetzungen
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Anwendungsbeispiele Englisch
  • On the Nascom 2, this included a connection to the /NMI (non-maskable interrupt) signal.
  • In computing, a non-maskable interrupt (NMI) is a hardware interrupt that standard interrupt-masking techniques in the system cannot ignore.
  • Any value written to NMIRES resets the bits in NMIST which indicate the reason for the most recent Non-Maskable Interrupt.
  • It provided only floppy disk and Centronics parallel interfaces, plus a non-maskable interrupt button.
  • In addition to floppy-disk, parallel port printer interface and a "magic button" (see Non-maskable interrupt), it also offered twin joystick ports, Sinclair ZX Net-compatible network ports and an inhibit button for disabling the device.

  • The latter generated a non-maskable interrupt, freezing any software running on the Spectrum and allowing it to be saved to disk.
  • They are generally symptomatic of an error in ring 0 that is not trapped by an error handler in an operating system or a hardware-triggered non-maskable interrupt.
  • The Z80 also supports a non-maskable interrupt. The /NMI signal is on Pin 17 of the original 40 pin DIP package.
  • The processor's non-maskable interrupt (NMI) input is edge sensitive, which means that the interrupt is triggered by the falling edge of the signal rather than its level.
  • The hardware interrupt system supports a 4-bit interrupt priority input, which needed to be higher than the priority level stored in the status register (bits 12−15) in order for the interrupt request to be served.

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    Enthält Übersetzungen von der TU Chemnitz sowie aus Mr Honey's Business Dictionary (nur Englisch/Deutsch).
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